System-on-chip (SOC) designs refer to integrating components of a computer or other electronic system into a single integrated circuit (IC) chip. SOC designs can include digital, analog, mixed-signal hardware components. For example, an SOC can contain one or more processors, one or more timing components such as an oscillator, and/or one or more memory components such as read only memory (ROM), random access memory (RAM), erasable programmable read only memory (EPROM), and/or flash memory. In addition, SOC designs can be utilized in many electronic devices, such as cellular phones, smart cards, personal digital assistants (PDAs), electronic games, electronic organizers, thumb drives, as well as a multitude of other electronic devices.
SOC designs can be developed using various intellectual property (IP) components from various vendors in the industry, which can be memory components (flash memory, RAM, ROM, etc.) and/or other types of hardware components (e.g., processors, timing components, clock generators, etc.). In addition, designers of an SOC system can design their own IP components or blocks (e.g., memory components and/or hardware components). Software drivers can also be developed to control the memory components and/or hardware components contained in an SOC design, for example.
One of the steps in developing an SOC design is that of verification and/or modeling. Verification can involve simulating an SOC design to determine its logical correctness and its compliance to the specification before it is sent to a chip foundry, wherein a foundry can be a semiconductor manufacturer that fabricates semiconductor chips. Modeling can involve simulating an SOC design with various scenarios to improve design cost and/or performance. Hardware description languages (HDLs), such as Verilog and VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL), as well as other languages (e.g., verification and/or descriptive languages) such as SystemVerilog, SystemC and Vera, can be used for such simulation and verification, for example.
SOC designs have become more complex over the years due to, in part, the ability to fit more memory components and hardware components into a single chip and because tools have been developed that can handle the inherent complexities associated with the more complex designs (e.g., SOC designs) regarding the simulation and verification of the designs. In particular, the verification (e.g., determining the logical correctness of a design) of an SOC design has become very complex and time consuming because of the number and complexity of hardware components that can be associated with an SOC design. For example, up to and even more than 70% of the time and energy associated with creating an SOC design can be spent on verification because of, in part, the increased complexity of SOC designs.
During the development of an SOC design, various hardware components can be developed and/or finished at different stages of the design (e.g., staggered development). However, this staggered development of hardware components can create difficulties in overall SOC verification. Specifically, it is often necessary to compile all of the memory components and/or hardware components associated with an SOC design to verify overall system interconnectivity. Thus, it is often times difficult to test an SOC design without the hardware components that are not completed or that have not been received from an IP component vendor for a particular SOC design. In addition, it can be difficult to determine what size of memory component is optimal for a particular design (e.g., particularly during the early stages of a design).
Therefore, it is desirable to be able to perform simulation and verification on, at least in part, an SOC design while one or more of the hardware components associated with the design are not available to be inserted (e.g., instantiated) and be able to insert one or more different size memory models in place of a memory component into an SOC design, particularly during the early stages of the design process. Being able to test an SOC design prior to possessing all of the completed hardware components and use different size memory models in place of one or more memory components associated with the SOC design can result in higher productivity and/or lower design cost because verification and/or optimization can be performed earlier in a design process, thus enabling one to debug problems with the design and/or optimize the design earlier in the design process.